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Development / Other / RTflow 1.0
RTflow 1.0
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RTflow 1.0 Description
RTflow is a free, lightweight dataflow modelling tool for real-time systems, somewhat similar to tools like MathWorks Simulink, National Instruments LabVIEW and SystemBuild.
RTflow is a free, lightweight dataflow modelling tool for real-time systems, somewhat similar to tools like MathWorks Simulink, National Instruments LabVIEW and SystemBuild. In RTflow, you build your system in a graphical language that is both parallel and deterministic, so that threading and timing problems are completely avoided. You verify your model in a simulator that produces graphs of every variable in the system, which allows you to spot bugs and their causes effortlessly. Finally, you generate software (C, C or Java) or hardware (VHDL) code from the model, allowing for immediate implementation on your target platform. Main features: -Schematic editor. The primary modelling language in RTflow is a graphical block schematic language. The built-in primitive blocks allow for modelling of combinatorial and/or time-discrete reactive systems and can handle boolean, integer and real variables. A schematic can be compiled into a new block that can be used in other schematics, so that models can be built hierarchically. RTflow also comes with a library of standard blocks that are defined in the same schematic language. -Simulator. The model can be efficiently simulated in a basic simulator that allows both step-by-step execution and complete simulation of a given time interval. Single variables can be modified interactively during the simulation. The results are presented graphically. -C/C /Java code generator. The model can be translated into efficient C, C or Java code for implementation in a real-world application. The user supplies a template file where pre-defined keys will be replaced with statements and other semantic information. -VHDL code generator. The model can also be translated into VHDL for implementation on CPLD:s and FPGA:s. The decision whether to generate C or VHDL, that is, implement in software or hardware, can thus be made after the complete model has been designed. -Open file formats. The model and all associated settings and project files are human-readable XML files. The syntax and semantics are open and fully documented. -Extensible architecture. Internally, RTflow is built so that parsers, code generators and other pluggable functionality are completely separated from the main application kernel, which is again separated from its GUI. This allows for easy addition of new input/output languages and customer-specific tools as well as replacement of the GUI. -Fast, lightweight and easy to learn. Written in native C , RTflow compiles a medium-sized project in nearly no time, and the simulator executes up to ten million operations per second. It does not install any services or clutter the registry. The schematic language is intuitive and the GUI is simple and quick to use also on a computer with a small screen.
OS: Windows